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모리스 마노 컴퓨터 구조 연습문제 2장 해답 그림 (parallel transfer 등)
Chapter 2
2-1. TTL IC
(a) Inverters - 2 pins each 12 / 2 = 6 gates 7404
(b) 2-input XOR - 3 pins each 12 / 3 = 4 gates 7486
(c) 3-input OR - 4 pins each 12 / 4 = 3 gates
(d) 4-input AND - 5 pins each 12 / 5 = 2gates 7421
(e) 5-input NOR - 6 pins each 12 / 6 = 2gates 74260
(f) 8-input NAND - 9 pins 1gates 7430
(g) JK flip-flop - 6 pins each 12 / 6 = 2 FFs 74107
2-2.
(a) 74155 - Similar to two decoders as in Fig 2-2.
(b) 74157 - Similar to multiplexers of Fig 2-5.
(c) 74194 - Similar to register of Fig. 2-9.
(d) 74163 - Similar to counter of Fig. 2-11.
2-5. Remove the inverter from the E input in Fig. 2-2(a).
2-9. When the parallel load input = 1, the clock pulses go through the AND gate and the data inputs are loaded into the register. When the parallel load input = 0, the output of the AND gate remains at 0.
2-10. The buffer gate does not perform logic. it is used for signal ampliflcation of the clock input.
2-13. serial transfer : one bit at a time by shifting.
Parallel transfer : All bits at the same time.
Input serial data by shifting data in parallel. Input data with parallel load-output data by sifting.
2-18. After the count yeaches N-1 - 1001, the register loads 0000 from inputs.
2-23. 12 data inputs + 2 enable inputs + 8 data outputs + 2 for power = 24pins
모리스 마노 컴퓨터 구조 연습문제 2장 해답 그림 (parallel transfer 등)